1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory with hierarchical bit lines.
2. Description of the Related Art
Recent semiconductor technology has developed highly-integrated, large-capacity semiconductor memories. These memories must operate at a high speed and with low power consumption.
The capacity of semiconductor memories such as DRAMs is increasing. There are even 64- or 256-megabit DRAMs. To handle an enormous quantity of data and match with high-speed peripheral devices, these memories must operate at a high speed and with low power consumption. The low power consumption feature is particularly important when the memories are adopted for book-type personal computers and portable equipment driven by batteries.
To satisfy these requirements, semiconductor memories with hierarchical bit lines have been studied and proposed. In the related art, the hierarchical bit lines are built using multilayer metal wiring and include global bit lines and polysilicon or polycide local bit lines. The global bit lines are connected to the local bit lines through transfer gates. Among the transfer gates, only those for a memory cell array involving an accessed word line are turned ON, to reduce the capacitance and time constant of the bit lines.
In the related art, the local bit lines are connected to the global bit lines through the transfer gates which are arranged at one end of each local bit line. Note that the global bit lines are complementary signal lines.
When the level of a row address strobe signal is changed from high to low, a bit line reset signal is changed from a high-potential source voltage to a low-potential source voltage. If the local bit line select signal is set to select the corresponding local bit lines, these local bit lines are connected to the global bit lines. Thereafter, one of the word lines is selected, and the contents of a memory cell connected to the selected word line are transferred to the global bit lines through the local bit lines.
Since the transfer gates are arranged at one end of each the local bit line, the resistance and signal transmission time constant of each of the bit lines are large and elongate the read time. To shorten the read time in which a sufficient voltage difference is produced in the bit lines, the length of the local bit lines must be shortened and the number of the local bit lines must be increased. In addition, the number of the transfer gates, and of the signal lines for controlling the transfer gates, must be increased.
The semiconductor memory of the related art employs complementary global bit lines made of metal such as aluminum. The interval between the two global bit lines cannot be reduced due to a manufacturing limit, to thereby limit the degree of integration. The problems of the related art will be explained hereinafter, in detail, with reference to the accompanying drawings.